Sciweavers

710 search results - page 93 / 142
» Estimating design time for system circuits
Sort
View
ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
15 years 10 months ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
15 years 11 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
VLSID
2008
IEEE
117views VLSI» more  VLSID 2008»
16 years 6 months ago
Single Event Upset: An Embedded Tutorial
Abstract-- With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends su...
Fan Wang, Vishwani D. Agrawal
MEMICS
2010
15 years 15 days ago
Monitoring and Control of Temperature in Networks-on-Chip
Abstract. Increasing integration densities and the emergence of nanotechnology cause issues related to reliability and power consumption to become dominant factors for the design o...
Tim Wegner, Claas Cornelius, Andreas Tockhorn, Dir...
CASES
2003
ACM
15 years 11 months ago
A low-power accelerator for the SPHINX 3 speech recognition system
Accurate real-time speech recognition is not currently possible in the mobile embedded space where the need for natural voice interfaces is clearly important. The continuous natur...
Binu K. Mathew, Al Davis, Zhen Fang