501 search results - page 10 / 101 » Evaluating CMPs and Their Memory Architecture |
ISSS
1997
IEEE
13 years 11 months ago
1997
IEEE
Embedded processor-based systems allow for the tailoring of the on-chip memory architecture based on application-specific requirements. We present an analytical strategy for explo...
CASES
2007
ACM
13 years 11 months ago
2007
ACM
Recently dual-port SDRAM (DPSDRAM) architecture tailored for dual-processor based mobile embedded systems has been announced where a single memory chip plays the role of the local...
DDECS
2006
IEEE
14 years 1 months ago
2006
IEEE
—Parallel memory modules can be used to increase memory bandwidth and feed a processor with only necessary data. Arbitrary stride access capability with interleaved memories is d...
SIGMOD
1992
ACM
13 years 11 months ago
1992
ACM
: The use of non-volatile semiconductor memory within an extended storage hierarchy promises significant performance improvements for transaction processing. Although page-addressa...
ICPP
2009
IEEE
14 years 2 months ago
2009
IEEE
The multicore revolution is underway, bringing new chips introducing more complex memory architectures. Classical algorithms must be revisited in order to take the hierarchical me...