501 search results - page 11 / 101 » Evaluating CMPs and Their Memory Architecture |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...
ASPLOS
1991
ACM
13 years 11 months ago
1991
ACM
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...
ISCA
2000
IEEE
14 years 3 hour ago
2000
IEEE
Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on si...
IEEEPACT
2008
IEEE
14 years 2 months ago
2008
IEEE
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
IPPS
1999
IEEE
13 years 12 months ago
1999
IEEE
Parallel programming models should attempt to satisfy two conflicting goals. On one hand, they should hide architectural details so that algorithm designers can write simple, port...