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» Evaluating CMPs and Their Memory Architecture
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ISCA
2012
IEEE
270views Hardware» more  ISCA 2012»
11 years 10 months ago
Revisiting hardware-assisted page walks for virtualized systems
Recent improvements in architectural supports for virtualization have extended traditional hardware page walkers to traverse nested page tables. However, current twodimensional (2...
Jeongseob Ahn, Seongwook Jin, Jaehyuk Huh
ASPLOS
2012
ACM
12 years 3 months ago
Providing safe, user space access to fast, solid state disks
Emerging fast, non-volatile memories (e.g., phase change memories, spin-torque MRAMs, and the memristor) reduce storage access latencies by an order of magnitude compared to state...
Adrian M. Caulfield, Todor I. Mollov, Louis Alex E...
HPCA
2007
IEEE
14 years 2 months ago
An Adaptive Cache Coherence Protocol Optimized for Producer-Consumer Sharing
Shared memory multiprocessors play an increasingly important role in enterprise and scientific computing facilities. Remote misses limit the performance of shared memory applicat...
Liqun Cheng, John B. Carter, Donglai Dai
MICRO
2003
IEEE
125views Hardware» more  MICRO 2003»
14 years 28 days ago
WaveScalar
Silicon technology will continue to provide an exponential increase in the availability of raw transistors. Effectively translating this resource into application performance, how...
Steven Swanson, Ken Michelson, Andrew Schwerin, Ma...
CCGRID
2009
IEEE
14 years 2 months ago
Improving Parallel Write by Node-Level Request Scheduling
In a cluster of multiple processors or cpu-cores, many processes may run on each compute node. Each process tends to issue contiguous I/O requests for snapshot, checkpointing or s...
Kazuki Ohta, Hiroya Matsuba, Yutaka Ishikawa