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DAC
2005
ACM
14 years 11 months ago
Device and architecture co-optimization for FPGA power reduction
Device optimization considering supply voltage Vdd and threshold voltage Vt tuning does not increase chip area but has a great impact on power and performance in the nanometer tec...
Lerong Cheng, Phoebe Wong, Fei Li, Yan Lin, Lei He
ADHOC
2008
88views more  ADHOC 2008»
13 years 10 months ago
Safari: A self-organizing, hierarchical architecture for scalable ad hoc networking
As wireless devices become more pervasive, mobile ad hoc networks are gaining importance, motivating the development of highly scalable ad hoc networking techniques. In this paper...
Shu Du, Ahamed Khan, Santashil PalChaudhuri, Ansle...
INFOCOM
2009
IEEE
14 years 4 months ago
NetTube: Exploring Social Networks for Peer-to-Peer Short Video Sharing
—The recent three years have witnessed an explosion of networked video sharing, represented by YouTube, as a new killer Internet application. Their sustainable development howeve...
Xu Cheng, Jiangchuan Liu
HPCA
2006
IEEE
14 years 10 months ago
Phase characterization for power: evaluating control-flow-based and event-counter-based techniques
Computer systems increasingly rely on dynamic, phasebased system management techniques, in which system hardware and software parameters may be altered or tuned at runtime for dif...
Canturk Isci, Margaret Martonosi
ASPLOS
1991
ACM
14 years 1 months ago
Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors
The memory consistency model supported by a multiprocessor architecture determines the amount of buffering and pipelining that may be used to hide or reduce the latency of memory ...
Kourosh Gharachorloo, Anoop Gupta, John L. Henness...