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» Evaluating Hardware Compilation Techniques
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TVLSI
2002
102views more  TVLSI 2002»
15 years 4 months ago
Low-power data forwarding for VLIW embedded architectures
In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...
FPGA
2005
ACM
107views FPGA» more  FPGA 2005»
15 years 10 months ago
Instruction set extension with shadow registers for configurable processors
Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made...
Jason Cong, Yiping Fan, Guoling Han, Ashok Jaganna...
DSD
2010
IEEE
153views Hardware» more  DSD 2010»
15 years 4 months ago
Simulation of High-Performance Memory Allocators
—Current general-purpose memory allocators do not provide sufficient speed or flexibility for modern highperformance applications. To optimize metrics like performance, memory us...
José Luis Risco-Martín, José ...
112
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ISCA
1999
IEEE
87views Hardware» more  ISCA 1999»
15 years 9 months ago
Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs
Several ILP limit studies indicate the presence of considerable ILP across dynamically far-apart instructions in program execution. This paper proposes a hardware mechanism, dynam...
Sriram Vajapeyam, P. J. Joseph, Tulika Mitra
158
Voted
CAV
2012
Springer
270views Hardware» more  CAV 2012»
13 years 7 months ago
Automated Termination Proofs for Java Programs with Cyclic Data
Abstract. In earlier work, we developed a technique to prove termination of Java programs automatically: first, Java programs are automatically transformed to term rewrite systems...
Marc Brockschmidt, Richard Musiol, Carsten Otto, J...