1304 search results - page 17 / 261 » Evaluating Hardware Compilation Techniques |
CASES
2006
ACM
14 years 1 months ago
2006
ACM
Random access memory (RAM) is tightly-constrained in many embedded systems. This is especially true for the least expensive, lowest-power embedded systems, such as sensor network ...
EURODAC
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper describes VHDL compilation techniques, embodied in the Auriga compiler [3,14], which facilitate parallel or distributed simulation by embedding evaluation scheduling in...
DATE
2000
IEEE
14 years 3 days ago
2000
IEEE
This paper presents a methodology to retarget the technique of compiled simulation for Digital Signal Processors DSPs using the modeling language LISA. In the past, the principl...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
The evaluation of extra-functional properties of embedded systems, such as reliability, timeliness, and energy consumption, as well as dealing with uncertainty, e.g., in the timin...
ISCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Blocked-execution multiprocessor architectures continuously run atomic blocks of instructions — also called Chunks. Such architectures can boost both performance and software pr...