1304 search results - page 20 / 261 » Evaluating Hardware Compilation Techniques |
ITC
1995
IEEE
13 years 11 months ago
1995
IEEE
An experiment has been designed to evaluate multiple testing techniques for combinational circuits. To perform the experiment, a 25k gate CMOS Test Chip has been designed, manufac...
ITC
1995
IEEE
13 years 11 months ago
1995
IEEE
This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and tes...
ICCD
2001
IEEE
14 years 4 months ago
2001
IEEE
This paper introduces minimal subset evaluation (MSE) as a way to reduce time spent on large-structure warm-up during the fastforwarding portion of processor simulations. Warm up ...
FCCM
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper provides an evaluation of SGI® RASC™ RC100 technology from a computational science software developer’s perspective. A brute force implementation of a two-point an...
GECCO
2008
Springer
13 years 8 months ago
2008
Springer
This paper compares three common evolutionary algorithms and our modified GA, a Distributed Adaptive Genetic Algorithm (DAGA). The optimal approach is sought to adapt, in near rea...