An Experimental Chip to Evaluate Test Techniques: Chip and Experiment Design

An experiment has been designed to evaluate multiple testing techniques for combinational circuits. To perform the experiment, a 25k gate CMOS Test Chip has been designed, manufactured (5491 devices), and evaluated with over 300 tests. The chip contains five types of CUTs derived from functions in production ASICs.

• Type: Conference
• Year: 1995
• Where: ITC
• Authors: Piero Franco, William D. Farwell, Robert L. Stokes, Edward J. McCluskey
• Keywords: CMOS Test Chip, Combinational Circuits, Hardware, ITC 1995, Multiple Testing Techniques