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» Evaluating Hardware Compilation Techniques
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SENSYS
2009
ACM
14 years 2 months ago
Low-power clock synchronization using electromagnetic energy radiating from AC power lines
Clock synchronization is highly desirable in many sensor networking applications. It enables event ordering, coordinated actuation, energy-efficient communication and duty cyclin...
Anthony Rowe, Vikram Gupta, Ragunathan Rajkumar
WISEC
2009
ACM
14 years 2 months ago
Securing network access in wireless sensor networks
In wireless sensor networks, it is critical to restrict the network access only to eligible sensor nodes, while messages from outsiders will not be forwarded in the networks. In t...
Kun Sun, An Liu, Roger Xu, Peng Ning, W. Douglas M...
ASPDAC
2007
ACM
131views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Fast Flip-Chip Pin-Out Designation Respin by Pin-Block Design and Floorplanning for Package-Board Codesign
Deep submicron effects drive the complication in designing chips, as well as in package designs and communications between package and board. As a result, the iterative interface d...
Ren-Jie Lee, Ming-Fang Lai, Hung-Ming Chen
ISCA
2011
IEEE
269views Hardware» more  ISCA 2011»
12 years 11 months ago
Power management of online data-intensive services
Much of the success of the Internet services model can be attributed to the popularity of a class of workloads that we call Online Data-Intensive (OLDI) services. These workloads ...
David Meisner, Christopher M. Sadler, Luiz Andr&ea...
ISCA
2006
IEEE
144views Hardware» more  ISCA 2006»
13 years 7 months ago
Conditional Memory Ordering
Conventional relaxed memory ordering techniques follow a proactive model: at a synchronization point, a processor makes its own updates to memory available to other processors by ...
Christoph von Praun, Harold W. Cain, Jong-Deok Cho...