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» Evaluating Hardware Compilation Techniques
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ISQED
2006
IEEE
153views Hardware» more  ISQED 2006»
14 years 1 months ago
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
Chong Zhao, Sujit Dey
DATE
2005
IEEE
125views Hardware» more  DATE 2005»
14 years 1 months ago
Lightweight Multitasking Support for Embedded Systems using the Phantom Serializing Compiler
Embedded software continues to play an ever increasing role in the design of complex embedded applications. In part, the elevel of abstraction provided by a high-level programming...
André C. Nácul, Tony Givargis
MICRO
2005
IEEE
144views Hardware» more  MICRO 2005»
14 years 1 months ago
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardw...
Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vi...
DAGSTUHL
1996
13 years 9 months ago
A Uniform Approach for Compile-Time and Run-Time Specialization
As partial evaluation gets more mature, it is now possible to use this program transformation technique to tackle realistic languages and real-size application programs. However, t...
Charles Consel, Luke Hornof, François No&eu...
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
14 years 3 days ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis