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» Evaluating Hardware Compilation Techniques
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FPL
2009
Springer
154views Hardware» more  FPL 2009»
14 years 1 months ago
Compiler assisted runtime task scheduling on a reconfigurable computer
Multitasking reconfigurable computers with one or more reconfigurable processors are being used increasingly during the past few years. One of the major challenges in such systems...
Mojtaba Sabeghi, Vlad Mihai Sima, Koen Bertels
HPCA
1998
IEEE
14 years 1 months ago
Hardware for Speculative Run-Time Parallelization in Distributed Shared-Memory Multiprocessors
Run-time parallelization is often the only way to execute the code in parallel when data dependence information is incomplete at compile time. This situation is common in many imp...
Ye Zhang, Lawrence Rauchwerger, Josep Torrellas
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
14 years 3 months ago
Constructing portable compiled instruction-set simulators: an ADL-driven approach
Instruction set simulators are common tools used for the development of new architectures and embedded software among countless other functions. This paper presents a framework th...
Joseph D'Errico, Wei Qin
CGO
2003
IEEE
14 years 2 months ago
Dynamic Trace Selection Using Performance Monitoring Hardware Sampling
Optimizing programs at run-time provides opportunities to apply aggressive optimizations to programs based on information that was not available at compile time. At run time, prog...
Howard Chen, Wei-Chung Hsu, Dong-yuan Chen
MICRO
2005
IEEE
126views Hardware» more  MICRO 2005»
14 years 2 months ago
Cost Sensitive Modulo Scheduling in a Loop Accelerator Synthesis System
Scheduling algorithms used in compilers traditionally focus on goals such as reducing schedule length and register pressure or producing compact code. In the context of a hardware...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...