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» Evaluating Hardware Compilation Techniques
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ICCAD
2003
IEEE
170views Hardware» more  ICCAD 2003»
14 years 5 months ago
Evaluation of Placement Techniques for DNA Probe Array Layout
DNA probe arrays have emerged as a core genomic technology that enables cost-effective gene expression monitoring, mutation detection, single nucleotide polymorphism analysis and ...
Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu ...
IRREGULAR
1995
Springer
14 years 15 days ago
Run-Time Techniques for Parallelizing Sparse Matrix Problems
Sparse matrix problems are di cult to parallelize e ciently on message-passing machines, since they access data through multiple levels of indirection. Inspector executor strategie...
Manuel Ujaldon, Shamik D. Sharma, Joel H. Saltz, E...
IFIPPACT
1994
13 years 10 months ago
Exploiting the Parallelism Exposed by Partial Evaluation
: We describe an approach to parallel compilation that seeks to harness the vast amount of ne-grain parallelism that is exposed through partial evaluation of numerically-intensive ...
Rajeev J. Surati, Andrew A. Berlin
LCTRTS
2007
Springer
14 years 3 months ago
Tetris: a new register pressure control technique for VLIW processors
The run-time performance of VLIW (very long instruction word) microprocessors depends heavily on the effectiveness of its associated optimizing compiler. Typical VLIW compiler pha...
Weifeng Xu, Russell Tessier
MICRO
2006
IEEE
135views Hardware» more  MICRO 2006»
14 years 3 months ago
Support for High-Frequency Streaming in CMPs
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
Ram Rangan, Neil Vachharajani, Adam Stoler, Guilhe...