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» Evaluating Hardware Compilation Techniques
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SASP
2009
IEEE
222views Hardware» more  SASP 2009»
15 years 11 months ago
A memory optimization technique for software-managed scratchpad memory in GPUs
—With the appearance of massively parallel and inexpensive platforms such as the G80 generation of NVIDIA GPUs, more real-life applications will be designed or ported to these pl...
Maryam Moazeni, Alex A. T. Bui, Majid Sarrafzadeh
IOLTS
2002
IEEE
99views Hardware» more  IOLTS 2002»
15 years 9 months ago
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques
This paper proposes a new solution for the diagnosis of faults into embedded RAMs, currently under evaluation within STMicroelectronics. The proposed scheme uses dedicated circuit...
Davide Appello, Alessandra Fudoli, Vincenzo Tancor...
DATE
2000
IEEE
88views Hardware» more  DATE 2000»
15 years 8 months ago
Free MDD-Based Software Optimization Techniques for Embedded Systems
Embedded systems make a heavy use of software to perform Real-Time embedded control tasks. Embedded software is characterized by a relatively long lifetime and by tight cost, perf...
Chunghee Kim, Luciano Lavagno, Alberto L. Sangiova...
ISLPED
1997
ACM
116views Hardware» more  ISLPED 1997»
15 years 8 months ago
Power reduction techniques for a spread spectrum based correlator
This paper presents the design of a low power spread spectrum correlator. We look at two major approaches and evaluate the best alternative for power reduction. We first consider...
David Garrett, Mircea R. Stan
DAC
2001
ACM
16 years 5 months ago
MetaCores: Design and Optimization Techniques
Currently, hardware intellectual property (IP) is delivered at vels of abstraction: hard, firm, and soft. In order to further enhance performance, efficiency, and flexibility of I...
Seapahn Meguerdichian, Farinaz Koushanfar, Advait ...