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» Evaluating Hardware Compilation Techniques
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CASES
2008
ACM
15 years 6 months ago
Control flow optimization in loops using interval analysis
We present a novel loop transformation technique, particularly well suited for optimizing embedded compilers, where an increase in compilation time is acceptable in exchange for s...
Mohammad Ali Ghodrat, Tony Givargis, Alex Nicolau
CGO
2007
IEEE
15 years 10 months ago
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping
The demand for high performance has driven acyclic computation accelerators into extensive use in modern embedded and desktop architectures. Accelerators that are ideal from a sof...
Amir Hormati, Nathan Clark, Scott A. Mahlke
ATS
2010
IEEE
239views Hardware» more  ATS 2010»
14 years 11 months ago
Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level
In recent technology nodes, reliability is considered a part of the standard design flow at all levels of embedded system design. While techniques that use only low-level models at...
Michael A. Kochte, Christian G. Zoellin, Rafal Bar...
DYNAMO
2000
110views more  DYNAMO 2000»
15 years 5 months ago
Machine-adaptable dynamic binary translation
Dynamic binary translation is the process of translating and optimizing executable code for one machine to another at runtime, while the program is "executing" on the ta...
David Ung, Cristina Cifuentes
MICRO
1999
IEEE
102views Hardware» more  MICRO 1999»
15 years 8 months ago
Evaluation of a High Performance Code Compression Method
Compressing the instructions of an embedded program is important for cost-sensitive low-power control-oriented embedded computing. A number of compression schemes have been propos...
Charles Lefurgy, Eva Piccininni, Trevor N. Mudge