1304 search results - page 86 / 261 » Evaluating Hardware Compilation Techniques |
162
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ISSS
2000
IEEE
15 years 8 months ago
2000
IEEE
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
117
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ISCA
2005
IEEE
15 years 10 months ago
2005
IEEE
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Up to now, system designers have prim...
121
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ITC
1998
IEEE
15 years 8 months ago
1998
IEEE
This paper presents a novel technique to evaluate the noncontrollability measures of state registers for partial scan design. Our model uses implicit techniques for finite state ma...
152
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PPDP
2005
Springer
15 years 10 months ago
2005
Springer
The paper develops a self-tuning resource aware partial evaluation technique for Prolog programs, which derives its own control strategies tuned for the underlying computer archit...
131
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IEEEPACT
2003
IEEE
15 years 9 months ago
2003
IEEE
This paper analyzes an Intel Pentium 4 hyper-threading processor. The focus is to understand its performance and the underlying reasons behind that performance. Particular attenti...