1304 search results - page 9 / 261 » Evaluating Hardware Compilation Techniques |
155
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ASPLOS
2010
ACM
15 years 11 months ago
2010
ACM
In this paper we evaluate the atomic region compiler abstraction by incorporating it into a commercial system. We find that atomic regions are simple and intuitive to integrate i...
138
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ICPPW
2005
IEEE
15 years 10 months ago
2005
IEEE
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
152
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ISPDC
2010
IEEE
15 years 3 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
154
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IEEEPACT
2005
IEEE
15 years 10 months ago
2005
IEEE
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...
137
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FPL
2007
Springer
15 years 10 months ago
2007
Springer
The aim of the hArtes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedd...