1304 search results - page 9 / 261 » Evaluating Hardware Compilation Techniques |
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
In this paper we evaluate the atomic region compiler abstraction by incorporating it into a commercial system. We find that atomic regions are simple and intuitive to integrate i...
ICPPW
2005
IEEE
14 years 1 months ago
2005
IEEE
Thread-level speculation is a technique that brings thread-level parallelism beyond the data-flow limit by executing a piece of code ahead of time speculatively before all its inp...
ISPDC
2010
IEEE
13 years 6 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
IEEEPACT
2005
IEEE
14 years 1 months ago
2005
IEEE
Helper threading is a technique that utilizes a second core or logical processor in a multi-threaded system to improve the performance of the main thread. A helper thread executes...
FPL
2007
Springer
14 years 1 months ago
2007
Springer
The aim of the hArtes project is to facilitate and automate the rapid design and development of heterogeneous embedded systems, targeting a combination of a general purpose embedd...