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ISPASS
2007
IEEE
15 years 10 months ago
Cross Binary Simulation Points
Architectures are usually compared by running the same workload on each architecture and comparing performance. When a single compiled binary of a program is executed on many diff...
Erez Perelman, Jeremy Lau, Harish Patil, Aamer Jal...
MICRO
2005
IEEE
130views Hardware» more  MICRO 2005»
15 years 10 months ago
Exploiting Vector Parallelism in Software Pipelined Loops
An emerging trend in processor design is the addition of short vector instructions to general-purpose and embedded ISAs. Frequently, these extensions are employed using traditiona...
Samuel Larsen, Rodric M. Rabbah, Saman P. Amarasin...
ASPLOS
2006
ACM
15 years 10 months ago
Introspective 3D chips
While the number of transistors on a chip increases exponentially over time, the productivity that can be realized from these systems has not kept pace. To deal with the complexit...
Shashidhar Mysore, Banit Agrawal, Navin Srivastava...
ISPASS
2005
IEEE
15 years 10 months ago
On the Scalability of 1- and 2-Dimensional SIMD Extensions for Multimedia Applications
SIMD extensions are the most common technique used in current processors for multimedia computing. In order to obtain more performance for emerging applications SIMD extensions ne...
Friman Sánchez, Mauricio Alvarez, Esther Sa...
GLVLSI
2009
IEEE
164views VLSI» more  GLVLSI 2009»
15 years 11 months ago
Capturing topology-level implications of link synthesis techniques for nanoscale networks-on-chip
In the context of nanoscale networks-on-chip (NoCs), each link implementation solution is not just a specific synthesis optimization technique with local performance and power im...
Daniele Ludovici, Georgi Nedeltchev Gaydadjiev, Da...