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» Evaluating Run-Time Techniques for Leakage Power Reduction
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ISCAPDCS
2007
13 years 9 months ago
Evaluation of architectural support for speech codecs application in large-scale parallel machines
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
Naeem Zafar Azeemi
FPL
2009
Springer
152views Hardware» more  FPL 2009»
14 years 7 days ago
Clock gating architectures for FPGA power reduction
Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock si...
Safeen Huda, Muntasir Mallick, Jason H. Anderson
HPCA
2002
IEEE
14 years 8 months ago
Power Issues Related to Branch Prediction
This paper explores the role of branch predictor organization in power/energy/performance tradeoffs for processor design. We find that as a general rule, to reduce overall energy ...
Dharmesh Parikh, Kevin Skadron, Yan Zhang, Marco B...
ASYNC
2005
IEEE
112views Hardware» more  ASYNC 2005»
14 years 1 months ago
Request-Driven GALS Technique for Wireless Communication System
A Globally Asynchronous - Locally Synchronous (GALS) technique for application in wireless communication systems is proposed and evaluated. The GALS wrappers are based on a reques...
Milos Krstic, Eckhard Grass, Christian Stahl
ICCD
2007
IEEE
99views Hardware» more  ICCD 2007»
13 years 11 months ago
Power reduction of chip multi-processors using shared resource control cooperating with DVFS
This paper presents a novel power reduction method for chip multi-processors (CMPs) under real-time constraints. While the power consumption of processing units (PUs) on CMPs can ...
Ryo Watanabe, Masaaki Kondo, Hiroshi Nakamura, Tak...