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EMSOFT
2006
Springer
14 years 16 days ago
Compiler-assisted leakage energy optimization for clustered VLIW architectures
Miniaturization of devices and the ensuing decrease in the threshold voltage has led to a substantial increase in the leakage component of the total processor energy consumption. ...
Rahul Nagpal, Y. N. Srikant
CODES
2006
IEEE
14 years 2 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
14 years 3 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
CODES
2005
IEEE
14 years 2 months ago
Designing real-time H.264 decoders with dataflow architectures
High performance microprocessors are designed with generalpurpose applications in mind. When it comes to embedded applications, these architectures typically perform controlintens...
Youngsoo Kim, Suleyman Sair
COMPSAC
2002
IEEE
14 years 1 months ago
Design and Implementation of a Network Application Architecture for Thin Clients
This paper explores the issues and the techniques of enabling multimedia applications for the thin client computing. A prototype of a video communication system based on H.323 fam...
Chia-Chen Kuo, Ping Ting, Ming-Syan Chen, Jeng-Chu...