38 search results - page 6 / 8 » Evaluating Techniques for Exploiting Instruction Slack |
APCSAC
2005
IEEE
14 years 1 months ago
2005
IEEE
Conditional branch induced control hazards cause significant performance loss in modern out-of-order superscalar processors. Dynamic branch prediction techniques help alleviate th...
SC
1992
ACM
13 years 11 months ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
VLDB
2005
ACM
14 years 25 days ago
2005
ACM
Simultaneous multithreading (SMT) allows multiple threads to supply instructions to the instruction pipeline of a superscalar processor. Because threads share processor resources,...
DIMVA
2009
13 years 8 months ago
2009
Drive-by download attacks are among the most common methods for spreading malware today. These attacks typically exploit memory corruption vulnerabilities in web browsers and brows...
MICRO
2008
IEEE
14 years 1 months ago
2008
IEEE
— As semiconductor processing techniques continue to scale down, transient faults, also known as soft errors, are increasingly becoming a reliability threat to high-performance m...