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» Evaluating kilo-instruction multiprocessors
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IPPS
2000
IEEE
13 years 12 months ago
Performance of On-Chip Multiprocessors for Vision Tasks
Abstract. Computer vision is a challenging data intensive application. Currently, superscalar architectures dominate the processor marketplace. As more transistors become available...
Yongwha Chung, K. Park, W. Hahn, Neungsoo Park, Vi...
ICS
1999
Tsinghua U.
13 years 11 months ago
The scalability of multigrain systems
Researchers have recently proposed coupling small- to mediumscale multiprocessors to build large-scale shared memory machines, known as multigrain shared memory systems. Multigrai...
Donald Yeung
ISCA
1998
IEEE
139views Hardware» more  ISCA 1998»
13 years 11 months ago
Simultaneous Multithreading: Maximizing On-Chip Parallelism
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
DATE
2009
IEEE
130views Hardware» more  DATE 2009»
14 years 2 months ago
Evaluating UML2 modeling of IP-XACT objects for automatic MP-SoC integration onto FPGA
—IP-XACT is a standard for describing intellectual property metadata for System-on-Chip (SoC) integration. Reesearchers have proposed visualizing and abstracting IP-XACT objects ...
Tero Arpinen, Tapio Koskinen, Erno Salminen, Timo ...
DSD
2009
IEEE
136views Hardware» more  DSD 2009»
13 years 11 months ago
An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload
Modern systems are able to put two or more processors on the same die (Chip Multiprocessors, CMP), each with its private caches, while the last level caches can be either private ...
Pierfrancesco Foglia, Francesco Panicucci, Cosimo ...