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» Evaluating kilo-instruction multiprocessors
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ICCD
2005
IEEE
97views Hardware» more  ICCD 2005»
14 years 4 months ago
Temperature-Sensitive Loop Parallelization for Chip Multiprocessors
In this paper, we present and evaluate three temperature-sensitive loop parallelization strategies for array-intensive applications executed on chip multiprocessors in order to re...
Sri Hari Krishna Narayanan, Guilin Chen, Mahmut T....
ECRTS
2006
IEEE
14 years 1 months ago
The Partitioned Scheduling of Sporadic Tasks According to Static-Priorities
A polynomial-time algorithm is presented for partitioning a collection of sporadic tasks among the processors of an identical multiprocessor platform with static-priority scheduli...
Nathan Fisher, Sanjoy K. Baruah, Theodore P. Baker
ISCAS
2006
IEEE
109views Hardware» more  ISCAS 2006»
14 years 1 months ago
Network-on-chip quality-of-service through multiprotocol label switching
Abstract— Providing Quality-of-Service (QoS) in networks-onchip (NoCs) will be an important consideration for the complex multiprocessor chips of the future. In this paper, we di...
Manho Kim, Daewook Kim, Gerald E. Sobelman
DAC
2004
ACM
14 years 8 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
ICDE
1999
IEEE
209views Database» more  ICDE 1999»
14 years 9 months ago
Parallel Classification for Data Mining on Shared-Memory Multiprocessors
We present parallel algorithms for building decision-tree classifiers on shared-memory multiprocessor (SMP) systems. The proposed algorithms span the gamut of data and task parall...
Mohammed Javeed Zaki, Ching-Tien Ho, Rakesh Agrawa...