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FCCM
2008
IEEE
114views VLSI» more  FCCM 2008»
14 years 2 months ago
Scaling Soft Processor Systems
As FPGA-based systems including soft-processors become increasingly common we are motivated to better understand the best way to scale the performance of such systems. In this pap...
Martin Labrecque, Peter Yiannacouras, J. Gregory S...
IPPS
2006
IEEE
14 years 1 months ago
Exploiting unbalanced thread scheduling for energy and performance on a CMP of SMT processors
This paper explores thread scheduling on an increasingly popular architecture: chip multiprocessors with simultaneous multithreading cores. Conventional multiprocessor scheduling,...
M. De Vuyst, Rakesh Kumar, Dean M. Tullsen
DATE
2003
IEEE
154views Hardware» more  DATE 2003»
14 years 26 days ago
Packetized On-Chip Interconnect Communication Analysis for MPSoC
Interconnect networks play a critical role in shared memory multiprocessor systems-on-chip (MPSoC) designs. MPSoC performance and power consumption are greatly affected by the pac...
Terry Tao Ye, Luca Benini, Giovanni De Micheli
ISCA
1998
IEEE
129views Hardware» more  ISCA 1998»
13 years 11 months ago
Memory System Characterization of Commercial Workloads
Commercial applications such as databases and Web servers constitute the largest and fastest-growing segment of the market for multiprocessor servers. Ongoing innovations in disk ...
Luiz André Barroso, Kourosh Gharachorloo, E...
ICPP
1990
IEEE
13 years 11 months ago
Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
Anoop Gupta, Wolf-Dietrich Weber, Todd C. Mowry