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» Evaluating kilo-instruction multiprocessors
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EUROSYS
2007
ACM
14 years 4 months ago
STMBench7: a benchmark for software transactional memory
Software transactional memory (STM) is a promising technique for controlling concurrency in modern multi-processor architectures. STM aims to be more scalable than explicit coarse...
Rachid Guerraoui, Michal Kapalka, Jan Vitek
DAC
2002
ACM
14 years 8 months ago
An energy saving strategy based on adaptive loop parallelization
In this paper, we evaluate an adaptive loop parallelization strategy (i.e., a strategy that allows each loop nest to execute using different number of processors if doing so is be...
Ismail Kadayif, Mahmut T. Kandemir, Mustafa Karak&...
HPCA
2007
IEEE
14 years 7 months ago
Illustrative Design Space Studies with Microarchitectural Regression Models
We apply a scalable approach for practical, comprehensive design space evaluation and optimization. This approach combines design space sampling and statistical inference to ident...
Benjamin C. Lee, David M. Brooks
DATE
2008
IEEE
131views Hardware» more  DATE 2008»
14 years 1 months ago
Parametric Throughput Analysis of Synchronous Data Flow Graphs
Synchronous Data Flow Graphs (SDFGs) have proved to be a very successful tool for modeling, analysis and synthesis of multimedia applications targeted at both single- and multiproc...
Amir Hossein Ghamarian, Marc Geilen, Twan Basten, ...
ICPP
2007
IEEE
14 years 1 months ago
Parallel Algorithms for Bayesian Indoor Positioning Systems
We present two parallel algorithms and their Unified Parallel C implementations for Bayesian indoor positioning systems. Our approaches are founded on Markov Chain Monte Carlo si...
Konstantinos Kleisouris, Richard P. Martin