Sciweavers

417 search results - page 72 / 84
» Evaluating kilo-instruction multiprocessors
Sort
View
DATE
2008
IEEE
138views Hardware» more  DATE 2008»
14 years 1 months ago
Dynamic Task Allocation Strategies in MPSoC for Soft Real-time Applications
This work evaluates task allocation strategies based on bin-packing algorithms in the context of multiprocessor systems-on-chip (MPSoCs) with task migration capabilities, running ...
Eduardo Wenzel Brião, Daniel Barcelos, Fl&a...
DATE
2007
IEEE
148views Hardware» more  DATE 2007»
14 years 1 months ago
Temperature aware task scheduling in MPSoCs
In deep submicron circuits, elevation in temperatures has brought new challenges in reliability, timing, performance, cooling costs and leakage power. Conventional thermal managem...
Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith...
IEEEPACT
2007
IEEE
14 years 1 months ago
Call-chain Software Instruction Prefetching in J2EE Server Applications
We present a detailed characterization of instruction cache performance for IBM’s J2EE-enabled web server, WebSphere Application Server (WAS). When running two J2EE benchmarks o...
Priya Nagpurkar, Harold W. Cain, Mauricio J. Serra...
MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
14 years 1 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
NCA
2007
IEEE
14 years 1 months ago
Improving Network Processing Concurrency using TCPServers
Exponentially growing bandwidth requirements and slowing gains in processor speeds have led to the popularity of multiprocessor architectures. Network stack parallelism is increas...
Aniruddha Bohra, Liviu Iftode