417 search results - page 83 / 84 » Evaluating kilo-instruction multiprocessors |
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
Dynamic software bug detection tools are commonly used because they leverage run-time information. However, they suffer from a fundamental limitation, the Path Coverage Problem: t...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
As the industry moves toward larger-scale chip multiprocessors, the need to parallelize applications grows. High inter-thread communication delays, exacerbated by over-stressed hi...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
SPAA
2005
ACM
14 years 1 months ago
2005
ACM
We describe a new class of utility-maximization scheduling problem with precedence constraints, the disconnected staged scheduling problem (DSSP). DSSP is a nonpreemptive multipro...