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EXPCS
2007
13 years 11 months ago
RiceNIC: a reconfigurable network interface for experimental research and education
The evaluation of new network server architectures is usually performed experimentally using either a simulator or a hardware prototype. Accurate simulation of the hardwaresoftwar...
Jeffrey Shafer, Scott Rixner
DSRT
2003
IEEE
14 years 23 days ago
An Agent Architecture for Network Support of Distributed Simulation Systems
Continued research into distributed agent-based systems and evolving web based technologies are opening up tremendous possibilities for the deployment of large scale and highly ex...
Robert Simon, Woan Sun Chang, J. Mark Pullen
FPGA
2008
ACM
161views FPGA» more  FPGA 2008»
13 years 9 months ago
Implementing high-speed string matching hardware for network intrusion detection systems
This paper presents high-throughput techniques for implementing FSM based string matching hardware on FPGAs. By taking advantage of the fact that string matching operations for di...
Atul Mahajan, Benfano Soewito, Sai K. Parsi, Ning ...
MICRO
2009
IEEE
147views Hardware» more  MICRO 2009»
14 years 2 months ago
Complexity effective memory access scheduling for many-core accelerator architectures
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
George L. Yuan, Ali Bakhoda, Tor M. Aamodt
MICRO
2003
IEEE
99views Hardware» more  MICRO 2003»
14 years 23 days ago
Power-driven Design of Router Microarchitectures in On-chip Networks
As demand for bandwidth increases in systems-on-a-chip and chip multiprocessors, networks are fast replacing buses and dedicated wires as the pervasive interconnect fabric for on-...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik