207 search results - page 24 / 42 » Evaluating the Performance of Software Cache Coherence |
WSC
1997
13 years 8 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
IPPS
1999
IEEE
13 years 11 months ago
1999
IEEE
Software DSM systems su er from the high communication and coherence-induced overheads that limit performance. This paper introduces our e orts in reducing system overheads of a h...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...
HPCA
2007
IEEE
14 years 7 months ago
2007
IEEE
Transactional Memory (TM) provides mechanisms that promise to simplify parallel programming by eliminating the need for locks and their associated problems (deadlock, livelock, pr...
CGO
2007
IEEE
14 years 1 months ago
2007
IEEE
Run-time compilation systems are challenged with the task of translating a program’s instruction stream while maintaining low overhead. While software managed code caches are ut...