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HIPEAC
2010
Springer
13 years 8 months ago
Improving Performance by Reducing Aborts in Hardware Transactional Memory
The optimistic nature of Transactional Memory (TM) systems can lead to the concurrent execution of transactions that are later found to conflict. Conflicts degrade scalability, a...
Mohammad Ansari, Behram Khan, Mikel Luján, ...
HPCA
2008
IEEE
14 years 7 months ago
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...
DSN
2009
IEEE
14 years 1 months ago
Decoupling Dynamic Information Flow Tracking with a dedicated coprocessor
Dynamic Information Flow Tracking (DIFT) is a promising security technique. With hardware support, DIFT prevents a wide range of attacks on vulnerable software with minimal perfor...
Hari Kannan, Michael Dalton, Christos Kozyrakis
MOBIHOC
2002
ACM
14 years 6 months ago
Performance evaluation of a fair backoff algorithm for IEEE 802.11 DFWMAC
Due to hidden terminals and a dynamic topology, contention among stations in an ad-hoc network is not homogeneous. Some stations are at a disadvantage in opportunity of access to ...
Zuyuan Fang, Brahim Bensaou, Yu Wang
CODES
2003
IEEE
14 years 8 hour ago
Accurate estimation of cache-related preemption delay
Multitasked real-time systems often employ caches to boost performance. However the unpredictable dynamic behavior of caches makes schedulability analysis of such systems difficul...
Hemendra Singh Negi, Tulika Mitra, Abhik Roychoudh...