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ISPASS
2007
IEEE
14 years 1 months ago
Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads
Address re-mapping techniques in so-called active memory systems have been shown to dramatically increase the performance of applications with poor cache and/or communication beha...
Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark Heinric...
DATE
2008
IEEE
156views Hardware» more  DATE 2008»
14 years 1 months ago
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications
Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in ...
Antonio Carlos Schneider Beck, Mateus B. Rutzig, G...
CASES
2007
ACM
13 years 10 months ago
An integrated ARM and multi-core DSP simulator
In this paper we describe the design and implementation of a flexible, and extensible, just-in-time ARM simulator designed to run co-operatively with a multi-core DSP simulator on...
Sharad Singhai, MingYung Ko, Sanjay Jinturkar, May...
NOCS
2007
IEEE
14 years 1 months ago
The Power of Priority: NoC Based Distributed Cache Coherency
The paper introduces Network-on-Chip (NoC) design methodology and low cost mechanisms for supporting efficient cache access and cache coherency in future high-performance Chip Mul...
Evgeny Bolotin, Zvika Guz, Israel Cidon, Ran Ginos...
LCTRTS
2000
Springer
13 years 10 months ago
Approximation of Worst-Case Execution Time for Preemptive Multitasking Systems
The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and su...
Matteo Corti, Roberto Brega, Thomas R. Gross