197 search results - page 8 / 40 » Evaluation of Computing in Memory Architectures for Digital ... |
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
In this paper, for the first time, we analyze non-quasistatic (NQS) effects during single-event upsets (SEUs) in deep-submicron (DSM) MOS devices, using extensive 2D device, BSIM...
ISNN
2005
Springer
14 years 28 days ago
2005
Springer
Abstract. Artificial Neural Networks (ANNs) and image processing requires massively parallel computation of simple operator accompanied by heavy memory access. Thus, this type of ...
ICIP
1999
IEEE
14 years 9 months ago
1999
IEEE
A new chip-set for video display processing in a consumer television or set-top box is presented. Key aspect of the chip-set is a high flexibility and programmability of multi-win...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
The paper presents an algorithm to determine the close-tosmallest possible data buffer sizes for arbitrary synchronous data flow (SDF) applications, such that we can guarantee the...
SBACPAD
2003
IEEE
14 years 20 days ago
2003
IEEE
This paper presents the cache configuration exploration of a programmable system, in order to find the best matching between the architecture and a given application. Here, prog...