104 search results - page 18 / 21 » Evaluation of design for reliability techniques in embedded ... |
CF
2009
ACM
14 years 2 months ago
2009
ACM
Recently, multi-core architectures with alternative memory subsystem designs have emerged. Instead of using hardwaremanaged cache hierarchies, they employ software-managed embedde...
CGO
2005
IEEE
14 years 1 months ago
2005
IEEE
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
VTS
2005
IEEE
14 years 1 months ago
2005
IEEE
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
FPL
2009
Springer
14 years 9 days ago
2009
Springer
Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets ...