SRAM leakage power dominates the total power of low duty-cycle applications, e.g., sensor nodes. Accordingly, leakage power reduction during data-retention in SRAM standby is ofte...
Animesh Kumar, Huifang Qin, Prakash Ishwar, Jan M....
Very Low Voltage (VLV) testing has been proposed to increase flaw detection in bulk silicon CMOS integrated circuits and this paper explores these and additional advantages in the...
Circuits optimized for minimum energy consumption operate typically in the subthreshold regime with ultra-low power-supply voltages. Speed of a subthreshold logic circuit is enhan...
The nonuniform substrate thermal profile and process variations are two major concerns in the present-day ultradeep submicrometer designs. To correctly predict performance/ leakage...
Deep-submicron designs have to take care of process variation effects as variations in critical process parameters result in large variations in access latencies of hardware compo...