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» Event-driven processor power management
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HPCA
2002
IEEE
14 years 8 months ago
The Minimax Cache: An Energy-Efficient Framework for Media Processors
This work is based on our philosophy of providing interlayer system-level power awareness in computing systems [26, 27]. Here, we couple this approach with our vision of multipart...
Osman S. Unsal, Israel Koren, C. Mani Krishna, Csa...
ISCA
2006
IEEE
145views Hardware» more  ISCA 2006»
13 years 7 months ago
Techniques for Multicore Thermal Management: Classification and New Exploration
Power density continues to increase exponentially with each new technology generation, posing a major challenge for thermal management in modern processors. Much past work has exa...
James Donald, Margaret Martonosi
ALGORITHMICA
2011
12 years 11 months ago
Average Rate Speed Scaling
Speed scaling is a power management technique that involves dynamically changing the speed of a processor. This gives rise to dual-objective scheduling problems, where the operati...
Nikhil Bansal, David P. Bunde, Ho-Leung Chan, Kirk...
VLSID
2009
IEEE
107views VLSI» more  VLSID 2009»
14 years 8 months ago
Temperature Aware Scheduling for Embedded Processors
Power density has been increasing at an alarming rate in recent processor generations resulting in high on-chip temperature. Higher temperature results in poor reliability and inc...
Ramkumar Jayaseelan, Tulika Mitra
ISCAS
2006
IEEE
124views Hardware» more  ISCAS 2006»
14 years 1 months ago
Systematic design flow for dynamic data management in visual texture decoder of MPEG-4
Abstract— There is a clear trend of future embedded systems in moving toward wireless, multimedia, multi-functional and ubiquitous applications. This emerges new challenges in th...
Alexandros Bartzas, Miguel Peón Quiró...