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» Event-driven processor power management
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CODES
2007
IEEE
14 years 2 months ago
Three-dimensional multiprocessor system-on-chip thermal optimization
3D stacked wafer integration has the potential to improve multiprocessor system-on-chip (MPSoC) integration density, performance, and power efficiency. However, the power density...
Chong Sun, Li Shang, Robert P. Dick
EMSOFT
2007
Springer
13 years 11 months ago
A unified practical approach to stochastic DVS scheduling
This paper deals with energy-aware real-time system scheduling using dynamic voltage scaling (DVS) for energy-constrained embedded systems that execute variable and unpredictable ...
Ruibin Xu, Rami G. Melhem, Daniel Mossé
ISCA
2003
IEEE
168views Hardware» more  ISCA 2003»
14 years 1 months ago
Temperature-Aware Microarchitecture
With power density and hence cooling costs rising exponentially, processor packaging can no longer be designed for the worst case, and there is an urgent need for runtime processo...
Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakuma...
CAL
2006
13 years 7 months ago
User-Driven Frequency Scaling
Abstract-- We propose and evaluate User-Driven Frequency Scaling (UDFS) for improved power management on processors that support Dynamic Voltage and Frequency Scaling (DVFS), e.g, ...
Arindam Mallik, Bin Lin, Gokhan Memik, Peter A. Di...
SIGCOMM
2009
ACM
14 years 2 months ago
PLUG: flexible lookup modules for rapid deployment of new protocols in high-speed routers
New protocols for the data link and network layer are being proposed to address limitations of current protocols in terms of scalability, security, and manageability. High-speed r...
Lorenzo De Carli, Yi Pan, Amit Kumar, Cristian Est...