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CORR
2010
Springer
189views Education» more  CORR 2010»
13 years 7 months ago
An Optimal Dynamic Mechanism for Multi-Armed Bandit Processes
We consider the problem of revenue-optimal dynamic mechanism design in settings where agents' types evolve over time as a function of their (both public and private) experien...
Sham M. Kakade, Ilan Lobel, Hamid Nazerzadeh
DATE
2009
IEEE
137views Hardware» more  DATE 2009»
14 years 2 months ago
Adaptive prefetching for shared cache based chip multiprocessors
Abstract—Chip multiprocessors (CMPs) present a unique scenario for software data prefetching with subtle tradeoffs between memory bandwidth and performance. In a shared L2 based ...
Mahmut T. Kandemir, Yuanrui Zhang, Ozcan Ozturk
ISCA
2010
IEEE
236views Hardware» more  ISCA 2010»
14 years 1 months ago
Elastic cooperative caching: an autonomous dynamically adaptive memory hierarchy for chip multiprocessors
Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-chip network usage. Furthermore, these platforms will run an heterogeneous mix of ap...
Enric Herrero, José González, Ramon ...
ACMMSP
2005
ACM
101views Hardware» more  ACMMSP 2005»
14 years 1 months ago
Transparent pointer compression for linked data structures
64-bit address spaces are increasingly important for modern applications, but they come at a price: pointers use twice as much memory, reducing the effective cache capacity and m...
Chris Lattner, Vikram S. Adve
DSN
2011
IEEE
12 years 7 months ago
LLS: Cooperative integration of wear-leveling and salvaging for PCM main memory
Phase change memory (PCM) has emerged as a promising technology for main memory due to many advan­ tages, such as better scalability, non-volatility and fast read access. However,...
Lei Jiang, Yu Du, Youtao Zhang, Bruce R. Childers,...