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ICCAD
1995
IEEE
136views Hardware» more  ICCAD 1995»
13 years 10 months ago
A controller-based design-for-testability technique for controller-data path circuits
This paper investigates the effect of the controller on the testability of sequential circuits composed of controllers and data paths. It is shown that even when both the controll...
Sujit Dey, Vijay Gangaram, Miodrag Potkonjak
ASPDAC
2004
ACM
72views Hardware» more  ASPDAC 2004»
14 years 4 days ago
Exploiting state encoding for invariant generation in induction-based property checking
— This paper focuses on checking safety properties for sequential circuits specified on the RTlevel. We study how different state encodings can be used to create a gate-level r...
Markus Wedler, Dominik Stoffel, Wolfgang Kunz
VTS
1996
IEEE
126views Hardware» more  VTS 1996»
13 years 11 months ago
Automatic test generation using genetically-engineered distinguishing sequences
A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test ge...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
ATS
2000
IEEE
134views Hardware» more  ATS 2000»
13 years 11 months ago
Fsimac: a fault simulator for asynchronous sequential circuits
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...
VTS
2000
IEEE
113views Hardware» more  VTS 2000»
13 years 11 months ago
Hidden Markov and Independence Models with Patterns for Sequential BIST
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
Laurent Bréhélin, Olivier Gascuel, G...