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ATS
1997
IEEE
87views Hardware» more  ATS 1997»
13 years 11 months ago
A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits
Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate in...
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
VTS
1997
IEEE
96views Hardware» more  VTS 1997»
13 years 11 months ago
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a sm...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
VTS
2003
IEEE
131views Hardware» more  VTS 2003»
13 years 12 months ago
Efficient Implication - Based Untestable Bridge Fault Identifier
: This paper presents a novel, low cost technique based on implications to identify untestable bridging faults in sequential circuits. Sequential symbolic simulation [1] is first p...
Manan Syal, Michael S. Hsiao, Kiran B. Doreswamy, ...
EH
2004
IEEE
163views Hardware» more  EH 2004»
13 years 10 months ago
Towards Evolvable Analog Artificial Neural Networks Controllers
This work deals with the design of analog circuits for Artificial Neural Networks (ANNs) controllers using an Evolvable Hardware (EHW) platform. ANNs are massively parallel system...
José Franco Machado do Amaral, Jorge Lu&iac...
VTS
1998
IEEE
97views Hardware» more  VTS 1998»
13 years 11 months ago
On the Identification of Optimal Cellular Automata for Built-In Self-Test of Sequential Circuits
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
Fulvio Corno, Nicola Gaudenzi, Paolo Prinetto, Mat...