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» Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs
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ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
14 years 21 hour ago
A clustering- and probability-based approach for time-multiplexed FPGA partitioning
Improving logic density by time-sharing, time-multiplexed FPGAs (TMFPGAs) have become an important research topic for reconfigurable computing. Due to the precedence and capacity ...
Mango Chia-Tso Chao, Guang-Ming Wu, Iris Hui-Ru Ji...
CODES
1994
IEEE
13 years 12 months ago
Towards a declarative framework for hardware-software codesign
We present an experimental framework for mapping declarative programs, written in a language known as Ruby, into various combinations of hardware and software. Strategies for para...
Wayne Luk, Teddy Wu
IJCAI
1997
13 years 9 months ago
Evolvable Hardware for Generalized Neural Networks
This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scal...
Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani...
FPL
2006
Springer
108views Hardware» more  FPL 2006»
13 years 11 months ago
Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices
This paper presents an implementation of a high-performance network application layer parser in FPGAs. At the core of the architecture resides a pattern matcher and a parser. The ...
James Moscola, Young H. Cho, John W. Lockwood
FCCM
1999
IEEE
134views VLSI» more  FCCM 1999»
14 years 1 days ago
Runlength Compression Techniques for FPGA Configurations
The time it takes to reconfigure FPGAs can be a significant overhead for reconfigurable computing. In this paper we develop new compression algorithms for FPGA configurations that...
Scott Hauck, William D. Wilson