453 search results - page 12 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
WSC
1997
13 years 9 months ago
1997
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
ASPLOS
1992
ACM
13 years 11 months ago
1992
ACM
Next generation computer systems will have gigabytes of physical memory and processors in the 200 MIPS range or higher. While this trend suggests that memory management for most p...
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
As transistors keep shrinking and on-chip data caches keep growing, static power dissipation due to leakage of caches takes an increasing fraction of total power in processors. Se...
HPCA
2001
IEEE
14 years 8 months ago
2001
IEEE
The performance of out-of-order processors increases with the instruction window size. In conventional processors, the effective instruction window cannot be larger than the issue...
ISORC
2011
IEEE
12 years 11 months ago
2011
IEEE
—Static cache analysis for data allocated on the heap is practically impossible for standard data caches. We propose a distinct object cache for heap allocated data. The cache is...