453 search results - page 16 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
Existing schemes for cache energy optimization incorporate a limited degree of dynamic associativity: either direct mapped or full available associativity (say 4-way). In this pap...
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
Dynamic reconfiguration techniques are widely used for efficient system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well...
PPOPP
2010
ACM
14 years 5 months ago
2010
ACM
Most modern Chip Multiprocessors (CMP) feature shared cache on chip. For multithreaded applications, the sharing reduces communication latency among co-running threads, but also r...
DAC
2003
ACM
14 years 26 days ago
2003
ACM
The increasing use of microprocessor cores in embedded systems as well as mobile and portable devices creates an opportunity for customizing the cache subsystem for improved perfo...
ECRTS
2008
IEEE
14 years 2 months ago
2008
IEEE
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...