453 search results - page 18 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
VLSI
2010
Springer
13 years 2 months ago
2010
Springer
Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. To overcome these...
IPPS
2003
IEEE
14 years 27 days ago
2003
IEEE
Concurrent multithreaded architectures exploit both instruction-level and thread-level parallelism through a combination of branch prediction and thread-level control speculation. ...
ICS
2001
Tsinghua U.
14 years 2 days ago
2001
Tsinghua U.
The caching behavior of multimedia applications has been described as having high instruction reference locality within small loops, very large working sets, and poor data cache p...
ECRTS
2009
IEEE
13 years 5 months ago
2009
IEEE
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
EUROPDS
1997
13 years 9 months ago
1997
In this paper, we follow a new path to arrive at the idea of a COMA — a Cache Only Memory Architecture. We show how the evolution of another architecture (ADARC) leads quite nat...