453 search results - page 23 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
HPCA
2006
IEEE
14 years 8 months ago
2006
IEEE
An integrated, hardware / software co-designed CISC processor is proposed and analyzed. The objectives are high performance and reduced complexity. Although the x86 ISA is targete...
GLVLSI
2008
IEEE
14 years 2 months ago
2008
IEEE
Phase-based tuning methodologies specialize system parameters for each application phase of execution. Parameters are varied during execution, as opposed to remaining fixed as in ...
APCSAC
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract. Scheduling algorithms significantly affect the performance of a realtime system. In systems with power constraints, context switches in a schedule result in wasted power ...
LCTRTS
2000
Springer
13 years 11 months ago
2000
Springer
The control system of many complex mechatronic products requires for each task the Worst Case Execution Time (WCET), which is needed for the scheduler's admission tests and su...
ECRTS
2005
IEEE
14 years 1 months ago
2005
IEEE
Cache memories have been extensively used to bridge the gap between high speed processors and relatively slower main memories. However, they are sources of predictability problems...