453 search results - page 40 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
ML
2002
ACM
13 years 8 months ago
2002
ACM
The execution order of a block of computer instructions on a pipelined machine can make a difference in running time by a factor of two or more. Compilers use heuristic schedulers...
HPCA
1998
IEEE
14 years 1 months ago
1998
IEEE
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
DAC
1999
ACM
14 years 1 months ago
1999
ACM
This paper presents a design methodology, called common-case computation (CCC), and new design automation algorithms for optimizing power consumption or performance. The proposed ...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
In this paper we propose a novel integrated circuit and architectural level technique to reduce leakage power consumption in high performance cache memories using single Vt (trans...
CASES
2008
ACM
13 years 11 months ago
2008
ACM
While technology advances have made MPSoCs a standard architecture for embedded systems, their applicability is increasingly being challenged by dramatic increases in the amount o...