453 search results - page 46 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
The number of functional errors escaping design verification and being released into final silicon is growing, due to the increasing complexity and shrinking production schedules ...
MICRO
1997
IEEE
14 years 1 months ago
1997
IEEE
Compiler optimizations are often driven by specific assumptions about the underlying architecture and implementation of the target machine. For example, when targeting shared-mem...
RTAS
2006
IEEE
14 years 2 months ago
2006
IEEE
Multicore architectures, which have multiple processing units on a single chip, are widely viewed as a way to achieve higher processor performance, given that thermal and power pr...
ICS
1999
Tsinghua U.
14 years 1 months ago
1999
Tsinghua U.
—This paper explores the use of compiler optimizations which optimize the layout of instructions in memory. The target is to enable the code to make better use of the underlying ...
MICRO
2003
IEEE
14 years 2 months ago
2003
IEEE
Wire delays are a major concern for current and forthcoming processors. One approach to attack this problem is to divide the processor into semi-independent units referred to as c...