453 search results - page 58 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
ICASSP
2008
IEEE
14 years 3 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
MICRO
1997
IEEE
14 years 1 months ago
1997
IEEE
Predicated execution is a promising architectural feature for exploiting instruction-level parallelism in the presence of control flow. Compiling for predicated execution involve...
ISCA
2005
IEEE
14 years 2 months ago
2005
IEEE
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
MICRO
2008
IEEE
14 years 3 months ago
2008
IEEE
Visualization, interaction, and simulation (VIS) constitute a class of applications that is growing in importance. This class includes applications such as graphics rendering, vid...
PC
2007
13 years 8 months ago
2007
We explore runtime mechanisms and policies for scheduling dynamic multi-grain parallelism on heterogeneous multi-core processors. Heterogeneous multi-core processors integrate con...