453 search results - page 75 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
ISPDC
2010
IEEE
13 years 7 months ago
2010
IEEE
—Super-scalar, out-of-order processors that can have tens of read and write requests in the execution window place significant demands on Memory Level Parallelism (MLP). Multi- ...
MICRO
1998
IEEE
14 years 1 months ago
1998
IEEE
The inherent instruction-level parallelism (ILP) of current applications (specially those based on floating point computations) has driven hardware designers and compilers writers...
CCGRID
2005
IEEE
14 years 2 months ago
2005
IEEE
Before an application modelled as a Directed Acyclic Graph (DAG) is executed on a heterogeneous system, a DAG mapping policy is often enacted. After mapping, the tasks (in the DAG...
IPPS
2003
IEEE
14 years 2 months ago
2003
IEEE
In this paper, we describe a compilation system that automates much of the process of performance tuning that is currently done manually by application programmers interested in h...
DAC
2002
ACM
14 years 9 months ago
2002
ACM
This paper addresses the problem of automatic generation of implementation software from high-level functional specifications in the context of embedded system on chip designs. So...