453 search results - page 77 / 91 » Execution and Cache Performance of the Scheduled Dataflow Ar... |
MICRO
2005
IEEE
14 years 2 months ago
2005
IEEE
— In this paper we investigate mapping stream programs (i.e., programs written in a streaming style for streaming architectures such as Imagine and Raw) onto a general-purpose CP...
MICRO
2000
IEEE
13 years 8 months ago
2000
IEEE
This paper demonstrates how an Instruction Path Coprocessor (I-COP) can be efficiently implemented using the PipeRench reconfigurable architecture. An I-COP is a programmable on-c...
ISCA
2006
IEEE
14 years 2 months ago
2006
IEEE
Transactional Memory (TM) simplifies parallel programming by allowing for parallel execution of atomic tasks. Thus far, TM systems have focused on implementing transactional stat...
SPAA
1996
ACM
14 years 28 days ago
1996
ACM
In this paper, we analyze the performance of parallel multithreaded algorithms that use dag-consistent distributed shared memory. Specifically, we analyze execution time, page fau...
DSN
2007
IEEE
14 years 3 months ago
2007
IEEE
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...