Sciweavers

98 search results - page 17 / 20
» Experience in the Automatic Parallelization of Four Perfect-...
Sort
View
ISCA
2011
IEEE
313views Hardware» more  ISCA 2011»
12 years 11 months ago
FabScalar: composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template
A growing body of work has compiled a strong case for the single-ISA heterogeneous multi-core paradigm. A single-ISA heterogeneous multi-core provides multiple, differently-design...
Niket Kumar Choudhary, Salil V. Wadhavkar, Tanmay ...
PPOPP
2005
ACM
14 years 1 months ago
Automated type-based analysis of data races and atomicity
Concurrent programs are notorious for containing errors that are difficult to reproduce and diagnose at run-time. This motivated the development of type systems that statically en...
Amit Sasturkar, Rahul Agarwal, Liqiang Wang, Scott...
COORDINATION
2004
Springer
14 years 1 months ago
Active Coordination in Ad Hoc Networks
The increasing ubiquity of mobile devices has led to an explosion in the development of applications tailored to the particular needs of individual users. As the research communit...
Christine Julien, Gruia-Catalin Roman
DAC
2008
ACM
13 years 9 months ago
Application mapping for chip multiprocessors
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...
Guangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. ...
HPDC
2007
IEEE
14 years 2 months ago
Feedback-directed thread scheduling with memory considerations
This paper describes a novel approach to generate an optimized schedule to run threads on distributed shared memory (DSM) systems. The approach relies upon a binary instrumentatio...
Fengguang Song, Shirley Moore, Jack Dongarra